Published on: 2021-02-14T00:27:36+00:00
The discussion revolves around the vulnerability of ASICs in test modes, particularly when key material is loaded into registers or caches. The risk can be mitigated by designing state machines and using flash memory to reload flip-flops that hold settings periodically. However, the vulnerability remains, making excessive caution necessary for cryptographic chips.In an email thread on Bitcoin-dev, concerns are raised about the use of repeater-buffers in ASICs and the need for test modes in mass production. Open-sourcing hardware design also has its risks, as attackers can target specific chip areas for ESD pulse. The importance of transparency in wallet ASICs is emphasized.There is a conversation between two individuals regarding the content of emails. Bryan Bishop expresses confusion, and the other individual apologizes for any confusion caused. They also provide a link to the threads for the bitcoin-dev mailing list.Luke Kenneth Casson Leighton asks for moderated messages to be sent to a different email address. Bryan replies that he cannot see Luke's February emails in the archives. The thread for the bitcoin-dev mailing list can be found on the Linux Foundation website.ZmnSCPxj requests Luke to forward moderated messages to a different email address. ZmnSCPxj discusses the use of scan mode and proposes a masking technique. The importance of being paranoid about test modes in digital circuitry is discussed. Solutions to prevent devices from being forced into test mode are suggested.The conversation covers various topics related to digital circuitry, including inverting buffers, open-source software and hardware RTL designs, test modes, and the importance of being paranoid about them. Solutions to prevent devices from being forced into test mode are provided.The conversation discusses the impact of power efficiency on Bitcoin mining. Increasing power efficiency does not reduce the actual energy consumed by mining. The "arms race" in mining could lead to hardware backdoors. The cost of lower geometries is high, and increasing power efficiency may not benefit anyone.The challenges of designing digital ASICs are discussed, along with the importance of formal correctness proofs and simulation testing. Adding general-purpose instructions that simplify algorithms is explored. Tool licensing costs, working with foundries, and reducing risk are also mentioned.ZmnSCPxj explains that focusing on power efficiency will not reduce energy consumption in Bitcoin mining. The rational choice for miners is to buy more units instead of reducing watt consumption. ZmnSCPxj expresses interest in eco-conscious blockchain and crypto-currency products.The author has experience designing digital ASICs and suggests that smaller geometries are only necessary for specific requirements. The challenges of manual layout and tool licensing costs are discussed. The LibreSOC Project aims to create transparently-openly-developed ASICs. The cost of producing ASICs varies with geometries. The focus should be on power-efficiency.Luke asks what people would like to see happen in regards to delivering to the wider bitcoin user community. Pavol Rusnak from SatoshiLabs offers to exchange ideas and provides a link to Tropic Square's website.The author has been discussing a transparently-developed ASIC/SoC with Kanzure for some time. NLnet has obtained funding, and the author has applied for the "Assure" Programme. The goal is to create fully transparently-openly-developed ASICs for cryptographic tasks. The author is interested in bridging the funding gap and delivering to the bitcoin user community.
Updated on: 2023-08-02T03:02:51.462708+00:00