Author: ZmnSCPxj 2021-02-14 00:27:36
Published on: 2021-02-14T00:27:36+00:00
The discussion revolves around the vulnerability of ASICs in test modes, especially when key material is loaded into registers or caches. An attacker can control the CPU clock and scan mode, thus making it possible to exfiltrate data from the scan chain registers, even if the chip is unable to execute algorithms. The risk can be mitigated by designing state machines that force unused states into known states and using flash memory to periodically reload flip-flops that hold settings. However, the vulnerability remains, which makes being excessively cautious for cryptographic chips a necessity.
Updated on: 2023-06-14T17:14:31.543440+00:00