Author: ZmnSCPxj 2021-02-03 02:06:46
Published on: 2021-02-03T02:06:46+00:00
The author of the text has experience designing digital ASICs but is limited to larger geometries and in SystemVerilog. They suggest that smaller geometries are only necessary if high performance/unit cost and performance/energy consumption ratios are required. The manual layout of devices impedes formal correctness proofs, as the netlist does not correspond exactly to an RTL that formal correctness can understand. While licenses for tools from trusted vendors like Synopsys or Cadence are expensive, funding towards open-source Icarus Verilog might be more feasible. However, foundries will not accept a netlist unless it was created by a synthesis tool from one of the major vendors. Foundry PDKs are now open source, making creating ASICs more feasible. The LibreSOC Project aims to create transparently-openly-developed ASICs that could perform cryptographic tasks such as mining and hardware wallet key protection. The project has received funding from NLnet and applied for the program "Assure," which was granted a new EU Horizon Grant. The cost of producing ASICs varies with the geometries and ranges from USD 20 million for a 7nm Custom ASIC to USD 100 million for full-custom silicon. However, the focus should be on power-efficiency: battery-operated hand-held devices at or below 3.5 watts. The LibreSOC Project is asking for feedback on what people would like to see happen and whether there is a realistic way to bridge (fund) the gap and actually deliver to the bitcoin user community. The project believes that it is a genuinely achievable goal to create fully transparently-openly-developed ASICs that could perform cryptographic tasks with a full audit trail even to the extent of having mathematical Formal Correctness Proofs.
Updated on: 2023-05-21T00:45:48.374868+00:00