Author: ZmnSCPxj 2021-02-11 08:20:54
Published on: 2021-02-11T08:20:54+00:00
The conversation started with the possibility of developing a tool that can parse a Verilog RTL design, generate a new version of it with one change and run a set of testcases around mutated variants of the design. However, the drawback of this approach is that just because an output is different does not mean the testcase actually checks that output. During the discussion, the difference between inverting buffers and non-inverting buffers was explained. It was also mentioned that smaller technologies consistently have lower raw output current driving capability due to their size. Additionally, it was highlighted that scan chain test generation using latches is impossible.Open-source software and hardware RTL designs were brought up, and it was emphasized that open-source synthesis tools are needed to synthesize them into netlists and then lay them out. The conversation then shifted towards discussing test modes and the need for them in mass production. However, it was pointed out that test modes can allow anyone to exfiltrate data from flip-flops. To prevent this, measures such as creating a small secure memory and explicitly laying it out "distributed" around the chip were suggested.The importance of being paranoid about test modes in digital circuitry was discussed since enough power-cycles and ESD noise can put them into unexpected states. Storing TESTMODE in a non-scan flip-flop was recommended, as targeted ESD can set TESTMODE even after normal operation. Using a byte pattern instead of a single bit to represent TESTMODE can make it harder for targeted ESD to force the device into test mode. To reduce the possibility of intermediate flip-flops outside the secure memory having sensitive key material or midstate data, solutions were suggested. One solution is to check the TESTMODE_PAD at reset. The code example provided in the context uses an always_ff loop to ensure that if RESET_N is not active low, then the testmode_ff value remains unchanged. In conclusion, the conversation covered various topics related to digital circuitry, including the use of inverting buffers, open-source software and hardware RTL designs, test modes, and the importance of being paranoid about them. The article also provided solutions to prevent devices from being forced into test mode due to targeted ESD or power cycles.
Updated on: 2023-06-14T17:16:30.921481+00:00