Author: Luke Kenneth Casson Leighton 2021-02-03 13:24:13
Published on: 2021-02-03T13:24:13+00:00
The conversation between ZmnSCPxj and Luke discusses the challenges of designing digital ASICs, specifically in relation to hardware wallet ASICs. ZmnSCPxj's experience is mostly with larger geometries and SystemVerilog, but as you approach lower geometries, analog design becomes more prevalent. They discuss the use of formal correctness proofs for netlist to RTL equivalence and simulation testing for RTL correctness. The conversation then shifts to exploring the possibility of adding general-purpose instructions that directly provide underlying mathematical principles and wrapping a Vector-Matrix Engine around them. This could potentially simplify algorithms to the point where readable C code compiles directly to opcodes that run faster than hand-optimized SIMD code using standard ISAs. Additionally, the conversation touches on tool licensing costs and recommendations for using multiple vendors, as well as the challenges of working with foundries and reducing risk.
Updated on: 2023-06-14T17:15:44.035844+00:00